1. Field of the Invention
This application claims the benefit of priority from Japanese Patent Application No. 2003-19696, filed on Jan. 29, 2003 which, is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device that includes a state transition mechanism for controlling the transition of an internal state and to a method for checking a state transition thereof. More particularly, embodiments consistent with the present invention relate to a semiconductor device that includes a nonvolatile memory unit to perform an autonomic function for a partial state transition by using a timer circuit and to a method for improving evaluation efficiency of the semiconductor device.
2. Description of Related Art
Generally, it takes a very long time to write or erase the memory cells for a semiconductor device that installs asynchronous type memory cells, such as a nonvolatile memory. Further, during the cell manufacturing processes, large variations are generated in the write and erase characteristics for each of the cells. Consequently, it is required to optimize a write time and an erase time for each of the cells. To do so, a conventional method is known for performing an automatic verification operation after writing or erasing to and from each cell.
FIG. 6 is a flowchart for explaining a conventional writing operation into nonvolatile memory cells in a semiconductor device. The writing operation includes an initializing step 101, a program step 102, a count updating step 1step 103, a verifying step 1step 104, a verification judging step 1step 105, a count judging step 106, a data update step 107, a post-treatment step 108 and an error setting step 109 in order to optimize the writing time for each of the cells.
When a writing command is inputted, at first, a writing address and writing data are loaded and latched at the initializing step 101. At the next program step 102, a writing voltage is supplied to the cell designated by the writing address based on the writing data. That is, an actual writing operation is performed by injecting electrons into a floating gate of the cell. Usually, the writing operation is simultaneously performed on a plurality of cells with units of 8 bits or 16 bits. Generally, it takes 1 to 2 micro-second (μs) for each of the writing operations.
After updating the writing count at the count updating step 103, the written data is read out at the verifying step 104. The read-out data and the writing data are compared at the verification judging step 105. Since a threshold value of a cell transistor varies due to the injected amount of electrons into the floating gate, when a sufficient amount of electrons has been injected, the value of the read-out data may coincide with the value writing data. On the contrary, if an insufficient amount of electrons were injected, the variation of the threshold value becomes small, and the value of the read-out data does not coincide with the value of the writing data.
In accordance with a result of this comparison, either one of the post-treatment step 108 and the count judging step 106 is selected. That is, if the value of the read-out data and the value of the writing data coincide (step 105, OK), the post-treatment step 108 is selected. If the value of the read-out data and the value of the writing data do not coincide (step 105, NG), the count judging step 106 is selected. For the post-treatment step 108 to be selected, each of the plurality of cells that were simultaneously written to needs to coincide such that each of the bits of the read-out data coincides with each of the bits of writing data. Accordingly, even when a cell does not coincide with just one bit, the count judging step 106 is selected.
The writing operation finishes by returning the voltage given to the cells into the initial condition at the post-treatment step 108.
At the count judging step 106, the writing count executed so far is compared to a predetermined value. If the executed writing count does not exceed the predetermined value (step 106, OK), the data updating step 107 is selected for performing a further electron injection operation. Then, the program step 102 is again repeated. In case the executed writing count exceeds the predetermined value (step 106, NG), the error setting step 109 is selected and the writing operation goes to the post-treatment step 108.
At the data updating step 107, the coincided bit to the write data is selected among the read-out data at the verify step 104. That is, cells that are injected with a sufficient amount of electrons into the respective floating gate are selected and the mask data is updated for preventing a writing operation from executing at the next program step 102. The aim of this step intends to stabilize operations of a circuit, as much as possible, such a read-out operation or an erasing operation by suppressing large variations of each threshold value for each of a cell transistor on each bit.
At the error setting step 109, it is recorded that the writing operation has not correctly finished, that is, the cell data was wrong, by setting an error flag. After that, the writing operation finishes through the post-treatment step 108.
Thus, for the writing operation, the program step 102 is repeated until all of the simultaneous writing cells of 8 bits or 16 bits are correctly wrote, except an error caused by exceeding the count. Consequently, it takes several 10 micro-seconds (μs) for each of the writing operations. This becomes a defect of a system installed in the semiconductor device since the writing operation takes a longer time than the operation time for another command cycle. Usually it needs for another command cycle taking about 100 nano-seconds (ns). To avoid this, it is usually designed so that the writing operation or the erasing operation can be suspended or stopped during the execution of an external interrupt command. When the operation is suspended, its address and data are stored in a register circuit so that the operation can restart at a later time. Further, in order to shorten a restarting lead time for inputting another command after the operation has been suspended by receiving an interrupt command, each of the steps illustrated in FIG. 6 is constructed so as to execute a necessary process for responding to such an interrupt command. Thus, to control such complicated operations, each step includes an internal state transiting mechanism so as to respond to an interrupt command in a shorter lead time, even when the interrupt command has been input at any time.
Meanwhile, it is a serious problem for evaluating such a condition of the semiconductor device to confirm all of the changes of the operations due to an interrupt command. Thus, even when an interrupt command occurs at any time during the several 10 μs, it must be guaranteed for the semiconductor device to operate correctly. Particularly, this is a serious problem for such a semiconductor device that allows asynchronous input of an external signal, because it needs to take an extensive amount of time to perform an evaluation and a failure analysis.
In an evaluation method that inputs an interrupt command by simply shifting timings, it is required for a writing operation to take an evaluation time of several 100 times to several 1,000 times. Actually, it is almost impossible to evaluate entire combinations of commands at all of the timing. Further, the evaluation method requires a failure reproduction, a failure analysis, or more particularly an internal signal wave observation to observe a signal wave that is only several nano-seconds (ns) among several 10 micro-seconds (10 μs). It is seriously difficult to generate trigger signals for this observation.
Moreover, it takes much longer for an erasing operation than for a writing operation. Usually, it takes about one second for every erasing operation. Thus, it becomes much more difficult for the erasing operation to perform such an evaluation or a failure analysis as mentioned above. As explained above, the conventional semiconductor device has serious problems for evaluating or analyzing interrupt commands during a writing operation or an erasing operation into nonvolatile memory cells. Thus, it takes an extensive amount of time to perform an evaluation or a failure analysis.